There is an ongoing quest to reduce the amount of time required to capture memory from an external memory module for processing by a microprocessor. At the same time, there is a competing desire to reduce the pin count in order to more efficiently design the integrated circuit chips from on which a memory module or microprocessor may be defined. Thus, some designs utilize a bi-directional bus between the memory module and the microprocessor. On a bi-directional bus, signal voltages may be held at mid-rail, or floating, in order to more efficiently switch the voltage between digital signal states.
However, holding the signal at the mid-rail state may result in voltage swings to zero or one due to noise on the bus. This increased noise makes it challenging for a memory controller to capture valid data on read cycles while avoiding false clocking due to strobe signals sitting at mid-rail when the bus is not being driven. If a storage element of an input first in first out (FIFO) buffer is enabled at an incorrect time, i.e., when a signal is still at mid-rail, false clocking can occur. The false clocking can result in capturing bad data and bad synchronization of the FIFO write pointer.
One attempt to address this shortcoming was the use of asynchronous FIFOs. However, this scheme required the use of complex/custom logic, which occupied valuable chip real estate. In addition, this custom logic further added to the delay of obtaining the requested data.
In light of the foregoing, it is desirable to implement a scheme for an improved data capture technique across a bi-directional bus that guarantees the availability of the correct data by enabling the input capture logic at the correct time to substantially eliminate false clocking issues.